1. Field of the Invention
The present invention relates to an integrated circuit device, particularly to an integrated circuit device which is designed to distribute and supply an external clock signal to an internal circuit of a chip.
2. Description of the Related Art
It is necessary to distribute and supply an external clock signal to an internal circuit of a chip for an integrated circuit device such as LSI. Generally, the internal circuit of the chip is composed of sequential circuits such as F/Fs (Flip-Flops). The F/F of the sequential circuit is designed to carry out data transfer in synchronization with the clock signal. For this purpose, it is necessary to supply the clock signal into respective F/Fs with a same timing. However, the difference in the supply timing of clock signal called clock skew is inherent in the design. Recently, especially, a permissible clock skew becomes small very much because of the increase in the clock signal frequency, and the reduction of clock skew is essential in a clock signal distribution network. The frequency of a clock signal used in a high-speed interface macro (circuit block) is higher than that in other portions, and the permissible clock skew is particularly severe.
The major factor of clock skew is the delay difference caused by the difference in a wiring line length to the F/Fs. As a clock signal distribution method to solve the clock skew, for example, a clock signal distribution system so-called H-tree is widely used in which the wiring line lengths to the F/Fs to operate in synchronism with the clock signal are geometrically equal to each other. An outline of such a clock signal distribution system is shown in FIG. 5.
In FIG. 5, high-speed interface macros 3 are arranged in the outer circumferential portion of a chip. An H-tree distribution system is composed of clock signal distribution wiring lines 5 and clock signal drivers 6. An external clock signal is delivered through a clock signal input buffer 2 and is separated into two clock signals by a first clock signal driver 6 through a PLL circuit 1 for phase adjustment. The separated clock signal is distributed to the high-speed interface macros 3 and an internal logic circuit area, which is not shown, by the H-tree distribution system.
As described above, the clock signal wiring lines are provided all over the surface of the chip from the internal logic circuit area to the high-speed interface macros in the clock signal distribution system shown in FIG. 5, Consequently, a delay from the PLL circuit 1 to the F/F within the macro increases, and the number of clock signal drivers 6 also increases. As a result, the clock signal distribution system is susceptible to the influence of clock skew due to crosstalk noise and jitter due to power supply noise, and has shortcomings that the clock skew tends to increase. As a result, the clock signal distribution system is susceptible to the influence of clock skew due to crosstalk noise and jitter due to power supply noise, and has shortcomings that the clock skew tends to increase.
Furthermore, when the wiring lines of the internal logic circuit are designed by using a tool such as a clock tree synthesis (CTS), the densities of wiring lines are different depending on parts of the chip. Therefore, even if the clock signal wiring lines are designed by using the H-tree structure to have same load and same wiring line length, the clock signal distribution system has shortcomings that skew is caused by the difference in the coupling capacitance with an wiring line in the internal logic circuit.
In the case of the H-tree, the clock signal is distributed all over the surface of the chip. Therefore, clock skew is easily caused due to manufacturing variations on the LSI chip surface. Also, the arrangement of clock signal wiring lines and the clock signal drivers is restricted depending on the form of the macros when the clock signal is distributed to plural kinds of high-speed interface macros different in form from each other.
In conjunction with the above description, a clock signal distribution circuit in a gate array is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-107316). The clock signal distribution circuit of this conventional example has a clock signal driver, circuit blocks and a clock signal bus for a clock signal to be supplied from the clock signal driver. The clock signal bus is arranged to surround the circuits.
Also, a logic integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 63-107316). In the logic integrated circuit of this conventional example, a chip area is divided into a plurality of blocks with same area. A clock signal distribution system is provided for every block to contain a clock signal input terminal and a buffer circuit connected with the input terminal. The clock signal distribution system is branched repetitively toward circuits provided in a tip portion of the block.
Also, a semiconductor logic integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-58205). In the semiconductor logic integrated circuit of this conventional example, a channel area exclusive for a clock signal wiring line is provided for the center of a semiconductor chip. An wiring line which supplies a clock signal to each section of an internal logic circuit is provided for the exclusive use channel area. A general signal line is not provided in the exclusive use channel area. Thus, it is prevented that the general signal line and the clock signal wiring line are arranged adjacent to each other and in parallel to each other. Therefore, it is possible to prevent noise on the signal and the clock signal through cross talk between the general signal line and the clock signal wiring line and clock skew in a clock distribution system due to the wiring line capacitance. Also, when an automatic wiring line designing is carried out by using a computer, the layout of the general signal lines and the gates are hardly restricted by providing clock wiring lines. Thus, the channel usage and the gate usage are improved.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-169914). The semiconductor integrated circuit of this conventional example is composed of logic calculating sections in each of which many logic gates are arranged, and an input/output section in which input/output buffers are arranged to surround the logic calculating section. A first clock signal path for transferring a clock signal is arranged to connect opposing central portions of the two logic calculating sections. The logic gates are arranged in a ring in a surrounded internal portion and an outer portion. A second clock signal path is connected to the first clock signal path and has branch lines extending into the outer portion.
Also, an integrated circuit and a method of designing wiring line are disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-317457). The integrated circuit of this conventional example has a plurality of partial circuits which are arranged in rectangular partial circuit arrangement areas with approximately same size on a semiconductor substrate and are composed of a plurality of basic logic circuits. Each of a plurality of clock signal supply sections is approximately in the center of a corresponding one of the partial circuit arrangement areas. The clock signal supply section supplies a clock signal to the basic logic circuit of the corresponding partial circuit to specify the timings of the operation based on a reference clock. The clock signal distribution line is separated into lines with a H-character shape with approximately equal lengths and the reference signal is distributed into the clock signal supply sections. The partial circuits, the clock signal supply sections, and the clock signal distribution line are formed on the semiconductor substrate, and carry out predetermined logic operation in synchronism with the reference clock signal. In order to make the reaching time of the clock signal from each clock signal supply section to the partial circuit equal approximately, a load section with no relation to the predetermined logic operation in addition to the basis logic circuit.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-P2000-35832A). In the semiconductor integrated circuit of this conventional example, a first clock signal distribution circuit outputs a clock signal onto a fixed clock signal wiring line and at least a second clock signal distribution circuit is connected with the fixed clock signal wiring line. The clock signal outputted from the second clock signal distribution circuit is distributed to sequential circuits of the semiconductor integrated circuit.
Also, a clock distribution circuit is disclosed in Japanese Laid Open Patent Application (JP-P 2000-200114A). The clock distribution circuit of this conventional example is composed of a plurality of a plurality of blocks each having a plurality of circuits. A first clock signal driver distributes a clock signal to each of the blocks. Second clock signal drivers are provided for each of the blocks to distribute the clock signal to the circuit of the block. First wiring lines connects the first clock signal driver and the second clock signal drivers for the clock signal with the same phase to reach the second clock signal drivers. A second wiring line is provided to connect the second clock signal driver to the circuit. The longest length of the second wiring line is smaller than a product of a permissible clock skew and a propagation velocity of electromagnetic wave to be transmitted on the second wiring line.
Also, an integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-P 2001-320022A). The integrated circuit of this conventional example is composed of a frequency dividing section for dividing a clock signal in frequency into 1/n (n is a positive integer) to generate a frequency-divided clock signal, and a plurality of driver circuits for outputting the frequency-divided clock signal onto a plurality of main wiring lines. A plurality of normal clock signal driver circuits have delay sections and driver sections. The delay section delays the frequency-divided clock signal to output a normal clock signal, and the driver section outputs the normal clock signal to a corresponding one of normal main wiring lines. A clock signal distribution circuit is composed of clock wiring lines for distributing the clock signal inputted from a clock signal input circuit, and a plurality of clock distribution relay buffers for receiving the frequency-divided and supplying the frequency-divided to the frequency dividing section and the driver circuits. A short circuit wiring line connect all outputs of the clock distribution relay buffers. A short circuit wiring line connects all outputs of the driver circuits. A short circuit wiring line connects all outputs of the normal clock signal driver circuits.